1 idtqs74fct2374t/at/ct high-speed cmos bus interface 8-bit register industrial temperature range january 2004 2004 integrated device technology, inc. dsc-5407/5 c idtqs74fct2374t/at/ct industrial temperature range high-speed cmos bus interface 8-bit register description: the idtqs74fct2374t is a high-speed cmos ttl-compatible 8-bit register with a buffered common clock and a buffered output enable control. the idtqs74fct2374t has a 25 ? resistor output that is useful for driving transmission lines and reducing system noise. the fct2374 is a non- inverting device. all inputs have clamp diodes for undershoot noise suppres- sion. all outputs have ground bounce suppression. outputs will not load an active bus when vcc is removed from the device. functional block diagram oe d cp q cp dx ox 25 ? 11 1 features: ? cmos power levels: <7.5mw static ? undershoot clamp diodes on all outputs ? true ttl input and output compatibility ? ground bounce controlled outputs ? reduced output swing of 0 to 3.5v ? built-in 25 ? ? ? ? ? series resistor outputs reduce reflection and other system noise ? std., a and c speed grades with 5.2ns t pd for c ?i ol = 12ma ? available in soic package
2 industrial temperature range idtqs74fct2374t/at/ct high-speed cmos bus interface 8-bit register soic top view 2 3 1 o 0 v cc 16 15 14 o 5 o 6 d 5 d 7 o 7 d 6 11 o 4 d 4 cp 19 18 20 17 13 12 oe 5 6 d 2 7 o 1 o 2 4 d 0 d 1 8 9 gnd 10 d 3 o 3 pin configuration symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +7 v t stg storage temperature ?65 to +150 c i out dc output current max sink current/pin 120 ma i ik input diode current, v in < 0 ?20 ma i ok output diode current, v out < 0 ?50 ma absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4 ? pf c out output capacitance v out = 0v 8 ? pf capacitance (t a = +25c, f = 1.0mhz) note: 1. this parameter is measured at characterization but not tested. pin description pin names i/o description dx i data inputs o x o data outputs c p | clock input oe i 3-state output enable (active low) function table (1) inputs internal outputs oe cp dx value qx ox function h l x ? z disable outputs h h x ? z disable outputs l l l l load input data l h h h enable outputs h l l z load input data h h h z enable outputs note: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance = low-to-high transition
3 idtqs74fct2374t/at/ct high-speed cmos bus interface 8-bit register industrial temperature range symbol parameter test conditions min. typ. (1) max. unit v ih input high level guaranteed logic high level 2 ? ? v v il input low level guaranteed logic low level ? ? 0.8 v ? v t input hysteresis v tlh - v thl for all inputs ? 0.2 ? v i ih input high current v cc = max. 0 v in v cc ?? 5a i il input low current i oz off-state output current (hi-z) v cc = max 0 v in v cc ?? 5a i or current drive v cc = max., v out = 2.0v (2) 50 ? ? m a v ic input clamp voltage v cc = min, i in = -18ma , t a = 25c (2) ? ?0.7 ?1.2 v v oh output high voltage v cc = min. i oh = -15ma 2.4 ? ? v v ol output low voltage v cc = min. i ol = 12ma ? ? 0.5 v r out (3) output resistance v cc = min. i oh = 12ma 15 21 35 ? dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v cc = 5.0v 5% notes: 1. typical values are at v cc = 5.0v, t a = 25c. 2. this parameter is measured at characterization but not tested. 3. r out changed on march 8, 2002. see rear page for more information. power supply characteristics following conditions apply unless otherwise specified: industrial: t a = -40c to +85c, v cc = 5.0v 5% symbol parameter test conditions (1) min. max. unit i cc quiescent power supply current v cc = max. ? 1.5 ma freq = 0 0v v in 0.2v or v cc - 0.2v v in vcc ? i cc supply current per input ttl inputs high v cc = max. ? 2 ma v in = 3.4v (2) freq = 0 i ccd supply current per input per mhz v cc = max. ? 0.25 ma/mhz outputs open and enabled one bit toggling 50% duty cycle other inputs at gnd or vcc (3,4) notes: 1. for conditions shown as min. or max., use the appropriate values specified under dc electrical characteristics. 2. per tll driven input (v in = 3.4v). 3. for flip-flops, i ccd is measured by switching one of the data input pins so that the output changes every clock cycle. this is a measurement of de vice power consumption only and does not include power to drive load capacitance or tester capacitance. 4. i c = i quiescent + i inputs + i dynamic i c = i cc + ? i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current ? i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an output transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz.
4 industrial temperature range idtqs74fct2374t/at/ct high-speed cmos bus interface 8-bit register fct2374t fct2374at fct2374ct symbol parameter (2) min. max. min. max. min. max. unit t plh propagation delay 2 10 2 6.5 2 5.2 ns t phl cp to o x t pzh output enable time 1.5 12.5 1.5 6.5 1.5 6.2 ns t pzl oe to y x t phz output disable time (3) 1.5 8 1.5 5.5 1.5 5 ns t plz oe to y x t s data setup time, dx to cp 2 ? 2 ? 1.5 ? ns t h data hold time, dx to cp 1.5 ? 1.5 ? 1 ? ns t w clock pulse width, high or low (3) 7? 5 ? 4? ns switching characteristics over operating range (1) notes: 1. c load = 50pf, r load = 500 ? unless otherwise noted. 2. minimums guaranteed but not tested. 3. this parameter is guaranteed by design but not tested.
5 idtqs74fct2374t/at/ct high-speed cmos bus interface 8-bit register industrial temperature range pulse generator r t d.u.t. v cc v in c l v out 50pf 500 ? 500 ? 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. fctl link fctl link fctl link fctl link fctl link test circuits and waveforms propagation delay enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable-high. 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns. test switch open drain disable low closed enable low all other tests open switch position definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. test circuits for all outputs
6 industrial temperature range idtqs74fct2374t/at/ct high-speed cmos bus interface 8-bit register ordering information so small outline ic (gull wing) high-speed cmos bus interface 8-bit register 2374t 2374at 2374ct 74 ?40c to +85c idtqs xx fct xxxx xx package device type temp. range corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com
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